Workshop on PCB Layout Design, Led by Robert Feranec, with Sierra as Participant
Robert Feranec's High-Speed PCB Board Layout Design Workshop at Levi's Stadium
Robert Feranec, a renowned PCB expert, led a two-day workshop on high-speed PCB board layout design at Levi's Stadium in Santa Clara, CA, on May 17th and 18th. The event, organised by Sierra Circuits, attracted 25 attendees who were eager to learn about the latest techniques in high-speed PCB design.
On the first day, Robert covered essential topics such as crosstalk, routing high-speed signals, differential pair routing, and getting the right impedance. He emphasized the importance of controlled impedance routing, minimizing signal noise and crosstalk, using short and direct signal paths, and paying attention to ground and power planes.
Robert also advised attendees to communicate with their manufacturer when using an Impedance Calculator, as they may need help with stack-up, layer ordering, and the number of layers. He encouraged attendees to ask their manufacturer for assistance when needed.
The workshop also featured a quiz for attendees to test their knowledge on PCB Board Layout Design Engineering, which was created by Sierra Circuits' Graphic Designer, Rachel.
On the second day, the focus shifted to DDR2/3 layout practice. Attendees were tasked with scheduling nets, adding T-points, creating pin pairs, correcting lengths, and routing traces. Robert advised against fully routing all tracks at once in DDR2/3 layout due to potential complications.
At the end of the two-day layout design training, attendees received a certification signed by Robert. The workshop materials, including a 251-page presentation by Robert, are available for those who missed the event or wish to review the content.
The workshop highlighted several common high-speed design rules, including careful selection of trace widths and dielectric materials for controlled impedance routing, spacing of differential pairs to minimize signal noise and crosstalk, and the use of solid ground planes to reduce electromagnetic interference (EMI) and ensure good return paths for high-speed signals.
These guidelines form the basis of high-speed PCB design to reduce issues like signal degradation, EMI, and timing errors in complex, high-frequency circuits. Robert Feranec’s tips particularly focus on matching track widths for impedance control and routing best practices to maintain signal quality.
Attendees were also given an exercise to calculate the trace width and space for a 100-ohm impedance. They were encouraged to use an impedance calculator for preliminary calculations and to ask the fabrication house for the accurate stack-up once a design is almost complete.
Overall, Robert Feranec's workshop provided attendees with valuable insights into high-speed PCB design, equipping them with the knowledge and skills to tackle complex, high-frequency circuits with confidence.
1. Attendees were advised to use an Impedance Calculator for preliminary calculations while designing high-speed PCBs, but were also encouraged to seek assistance from their manufacturer for accurate stack-up once the design is almost complete.
2. Along with discussing various high-speed PCB design techniques such as controlled impedance routing and minimizing signal noise, Robert Feranec's workshop emphasized the importance of utilizing technology like an Impedance Calculator to efficiently calculate trace widths and spaces for impedance control in high-frequency circuit design.
